1. Field of the Invention
This invention relates to data cache circuits, and more particularly, to a method, system, and computer program product for implementing a dual-addressable cache.
2. Description of Background
A cache is a high-speed array of recently-accessed data or other computer information and is typically indexed by an address. Certain caches, like translation caches (also known as translation-lookaside buffers (TLBs)), can have two viable indices, such as a virtual address index (before translation) and a real address index (after translation). If such an array is indexed by one type of address (e.g., virtual address), but a search or update is required based on the other type of address (e.g., real address), a linear search of the array is typically required in order to determine any occurrence of the desired address (in this case, the real address).
One solution is a content addressable memory (CAM) array, which refers to a large structure that provides a highly parallel lookup of the non-indexed address type. Unfortunately, CAMs are expensive to build, take up significant amounts of chip area, and usually have significant logic restrictions (e.g., ability to manipulate only a portion of the address) in order to make them practical. An alternative solution is to have two directories (i.e., arrays), each one indexed by one of the two address types, with updates of both arrays required in order to keep them synchronized. However, this solution, by definition, requires double the number of arrays, as well as a great deal of synchronization logic, which may not be practical.
What is needed, therefore, is a more efficient way to implement caches, in terms of ease of operation, as well as time and memory requirements.